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ASAHI KASEI
[AK4564]
AK4564
16bit CODEC with built-in ALC and MIC/HP/SPK-Amp
GENERAL DESCRIPTION
The AK4564 is a 16bit stereo CODEC with a built-in Microphone-Amp, Headphone-Amp and Speaker-Amp. AK4564 has new recording features, a digital equalizer for microphone inputs and a digital ALC (Automatic Level Control). The playback features also include LINEOUT-Amp, digital volume, Headphone-Amp and Speaker-Amp. The AK4564 suits a portable application with a built-in LCD and etc. The AK4564 is housed in a space-saving 48pin LQFP package.
FEATURE 1. Resolution: 16bits 2. Recording Function: * 4-Input Selector (Internal MIC, External MIC, LINE x 2) * Pre-Amp * Digital EQ/HPF/LPF * Digital ALC (Automatic Level Control) circuit * FADEIN / FADEOUT * Digital HPF for offset cancellation (fc=3.7Hz@fs=48kHz) * Enable mixing of BEEP signal 3. Playback Function * Digital De-emphasis Filter (tc = 50/15s, fs = 32kHz, 44.1kHz and 48kHz) * LINEOUT-Amp * Digital Volume: 0dB - 65.25dB, Mute * Headphone-Amp - Po: 5.3mW @ 16 (AVDD = 2.8V) * Speaker-Amp with built-in ALC - BTL Output - Po: 80mW @ 8 * Enable mixing of BEEP signal 4. Power Management 5. ADC characteristics (LIN ADC) * S/(N+D): 87dB, DR=S/N: 90dB 6. DAC characteristics (DAC LINEOUT-Amp) * S/(N+D): 82dB, DR=S/N: 88dB 7. Master Clock: 256fs/384fs 8. Sampling Rate: 8kHz 50kHz 9. Audio Data Interface Format: MSB-First, 2's compliment * ADC, DAC: 16bit MSB justified, 16bit LSB justified, I2S 10. Ta = -20 85 C 11. Power Supply Voltage * CODEC, Speaker-Amp: 2.6 3.6V * MIC/Headphone/LINEOUT-Amp: 2.6 5.5V 12. Power Supply Current * All Power On: 30.5mA 13. Package: 48pin LQFP, 0.5mm Pitch
MS0140-E-01 -1-
2002/07
ASAHI KASEI
[AK4564]
LIN1 LIN2
BEEP1
RIN2 RIN1
INTL Pre-Amp EXTL ADC MPWR MRF MVDD MVSS
MIC MIC
INTR Pre-Amp EXTR
MIC Power Supply MCLK LRCK EQ LPF HPF ALC1 Audio I/F Controller BCLK SDTI SDTO
ADC
AVDD AVSS VCOM
DVDD DVSS MUTE HVDD HVCM PDN
MUTET HPL HPR
DAC
DAC
OATT
HPP
SVDD SVSS
SPKP
AOUTP2
AOUTP1
ALC2 SPK
MIX
+2dBV
+2dBV Control Register I/F
Power Management BEEP2
LOUT2
ROUT2 LOUT1 ROUT1
CSN
CCLK
CDTI
Figure 1. AK4564 block diagram
MS0140-E-01 -2-
2002/07
ASAHI KASEI
[AK4564]
PIN/FUNCTION
No. Pin Name Power Supply 5 SVDD 6 SVSS 15 DVDD 16 DVSS 28 HVDD 30 HVCM 31 AVSS 32 AVDD 33 VCOM 41 MVSS 42 MVDD 43 MPWR 44 MRF Operation Clock 7 BCLK 8 MCLK 9 LRCK 13 SDTI 14 SDTO MIC Block 37 PREOR 38 PRENR 39 EXTR 40 INTR 45 INTL 46 EXTL 47 PRENL 48 PREOL Control Data Interface 10 CDTI 11 CSN 12 CCLK ADC Block 17 LIN1 19 RIN1 21 LIN2 23 RIN2 DAC Block 18 LOUT1 20 ROUT1 22 LOUT2 24 ROUT2 I/O O O O O I I I I O O I I I I I I O I I I I I I I O O O O FUNCTION Speaker Amp Power Supply Pin, +3.0V Speaker Amp Ground Pin Digital Power Supply Pin, +2.8V Digital Ground Pin Headphone-Amp, LINEOUT Power Supply Pin, +4.5V Headphone-Amp, LINEOUT Common Voltage Output Pin, 0.5 x HVDD Analog Ground Pin Analog Power Supply Pin, +2.8V Common Voltage Output Pin, 0.5 x AVDD MIC Amp Ground Pin MIC Amp Power Supply Pin, +2.8V MIC Power Supply Pin, 1.6V@MVDD=2.8V, Idd=3mA(max) MIC Power Supply Ripple Filter Pin Audio Serial Data Clock Pin Master Clock Input Pin Input/Output Channel Clock Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Rch Pre-Amp Output Pin Rch Pre-Amp Negative Input Pin Lch External MIC Input Pin Rch Internal MIC Input Pin Lch Internal MIC Input Pin Rch External MIC Input Pin Lch Pre-Amp Negative Input Pin Lch Pre-Amp Output Pin Control Data Input Pin Chip Select Pin Control Clock Input Pin Lch Line #1 Input Pin Rch Line #1 Input Pin Lch Line #2 Input Pin Rch Line #2 Input Pin Lch Line #1 Output Pin Rch Line #1 Output Pin Lch Line #2 Output Pin Rch Line #2 Output Pin
NOTE: All digital input pins must not be left floating.
MS0140-E-01 -3-
2002/07
ASAHI KASEI
[AK4564]
No. Pin Name Headphone Amp 26 HPL 27 HPR 29 MUTET Speaker Amp Block 1 SP0 3 SP1 34 MOUT 35 MIN Other Functions 2 4 MUTE PDN
I/O O O O O O O I I I I I
FUNCTION Lch Headphone Amp Output Pin Rch Headphone Amp Output Pin Headphone Amp MUTE Capacitor Pin Speaker Amp positive Output Pin Speaker Amp negative Output Pin Analog Mixing Output Pin ALC2 Input Pin Mute Pin "L": Normal Operation, "H" MUTE Reset & Power-down Pin "L": Reset & Power-down, "H": Normal Operation Beep Signal #2 Input Pin Beep Signal #1 Input Pin
25 BEEP2 36 BEEP1
NOTE: All digital input pins must not be left floating.
MS0140-E-01 -4-
2002/07
ASAHI KASEI
[AK4564]
n Ordering Guide
AK4564VQ AKD4564 -20 +85C 48pin LQFP (0.5mm pitch) Evaluation board for AK4564
n Pin layout
MPWR MVDD MVSS EXTR INTR PRENR 38 PREOL PRENL EXTL PREOR 37
INTL 45
48
47
46
44
MRF
43
42
41
40
39
SP0 MUTE SP1 PDN SVDD SVSS BCLK MCLK LRCK CDTI CSN CCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top View
36 35 34 33
BEEP1 MIN MOUT VCOM AVDD AVSS HVCM MUTET HVDD HPR HPL BEEP2
AK4564
32 31 30 29 28 27 26 25
ROUT1
MS0140-E-01 -5-
ROUT2
LOUT1
LOUT2
DVDD
DVSS
RIN1
SDTI
SDTO
RIN2
LIN1
LIN2
2002/07
ASAHI KASEI
[AK4564]
ABSOLUTE MAXIMUM RATING
(AVSS, DVSS, MVSS, SVSS=0V;Note 1) Parameter Symbol min max Units Power Supplies Analog 1 AVDD -0.3 6.0 V Analog 2 HVDD -0.3 6.0 V MIC MVDD -0.3 6.0 V Digital DVDD -0.3 6.0 V Speaker SVDD -0.3 6.0 V | DVSS - AVSS | (Note 2) GND1 0.3 V | MVSS - AVSS | (Note 2) GND2 0.3 V | SVSS - AVSS | (Note 2) GND3 0.3 V 10 Input Current (Any pins except supplies) IIN mA Analog Input Voltage (Note 3) VINA1 -0.3 AVDD+0.3 V (Note 4) VINA2 -0.3 MVDD+0.3 V Digital Input Voltage (Note 5) VIND -0.3 DVDD+0.3 V Ambient Temperature Ta -20 85 C Storage Temperature Tstg -65 150 C Pd1 500 mW Maximum Power Dissipation Ta=85C (Note 7) (Note 6) Ta=70C (Note 8) Pd2 700 mW Note 1. All voltage with respect to ground. Note 2. AVSS, DVSS, MVSS and SVSS must be connected to the same analog ground plane. Note 3. LIN1, RIN1, LIN2, RIN2, BEEP1, BEEP2 and MIN pins Note 4. EXTL, EXTR, INTL, INTR, PRENL and PRENR pins Note 5. MCLK, LRCK, BICK, SDTI, PDN, CSN, CCLK, CDTI and MUTE pins Note 6. Wiring density is 50% or more. Note 7. Headphone-Amp and Speaker-Amp shouldn't be powered up at the same time. The maximum power supply voltage of SVDD is 3.3V. Note 8. Headphone-Amp and Speaker-Amp can be powered up at the same time. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(AVSS, DVSS, MVSS, SVSS=0V;Note 1) Parameter Symbol min typ max Units Power Supplies Analog 1 AVDD 2.6 2.8 3.6 V Analog 2 HVDD 2.6 4.5 5.5 V MIC (Note 9) MVDD 2.6 or "AVDD - 0.1" 2.8 5.5 V Digital DVDD 2.6 2.8 AVDD V Speaker (Note 10) SVDD 2.6 3.0 3.3 or 3.6 V Note 1. All voltage with respect to ground. Note 9. Minimum value is higher value between 2.6V and "AVDD - 0.1"V. Note 10. When Ta (max) is 85C, SVDD (max) is 3.3V. Then Headphone-Amp and Speaker-Amp shouldn't be powered up at the same time. When Ta (max) is 70C, SVDD (max) is 3.6V. Then Headphone-Amp and Speaker-Amp can be powered-up at the same time.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0140-E-01 -6-
2002/07
ASAHI KASEI
[AK4564]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD, DVDD, MVDD=2.8V, SVDD=3.0V, HVDD=4.5V; AVSS, DVSS, MVSS, SVSS=0V; fs=48kHz; Input Frequency =1kHz; Measurement width=20Hz 20kHz, unless otherwise specified) Parameter Pre-Amp Characteristics: Input Resistance (INTL, INTR, EXTL, EXTR pins) Maximum Output Voltage (Note 11) Gain Load Resistance (Note 12) Load Capacitance (Note 13) MIC Power Supply Voltage Characteristics: MPWR pin Output Voltage (Output current = 0mA) (Note 14) Maximum Output Current ADC Analog Input Characteristics: ALC1 = OFF Resolution 16 bits Input Resistance (LIN1, RIN1, LIN2, RIN2 pins) 70 100 130 k Input Voltage (Note 15) (Note 16) -5.1 -4.3 -3.5 dBV (Note 15) (Note 17) -58.5 -57.7 -56.9 dBV S/(N+D) (-0.5dBFS) (Note 16) 78 88 dB (Note 18) 75 85 dB DR (-60dBFS, A-Weighted) (Note 16) 84 90 dB (Note 17) 57 61 dB S/N (A-Weighted) (Note 16) 84 90 dB (Note 17) 57 61 dB Interchannel Isolation (Note 16) 80 100 dB (Note 17) 50 70 dB Interchannel Gain Mismatch (Note 16) 0.5 dB (Note 17) 0.5 dB Note 11. Maximum output voltage is (0.6 x AVDD) Vpp. Note 12. Load resistance is the value of "Rf + Ri". (Refer to Figure 12) Note 13. When the output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. Note 14. When the output current is 0mA, the output voltage of MPWR pin is typically (MVDD - 1.2) V at MVDD=2.8V and typically (MVDD-1.4) V at MVDD=4.5V. When the output current is 3mA, the output voltage of MPWR pin is typically (MVDD - 1.5) V at MVDD=2.8V and typically (MVDD-1.7) V at MVDD=4.5V. Note 15. Input voltages are proportional to AVDD voltage. LIN1, RIN1, LIN2, RIN2 = (0.62 x AVDD) Vpp INTL, INTR, EXTL, EXTR = (0.0013 x AVDD) Vpp Note 16. Input from LIN1, RIN1, LIN2 or RIN2 pins. IVOL=0dB. Note 17. Input from INTL, INTR, EXTL or EXTR pins. Pre-Amp Gain = + 23.9dB, PRE = "1", IVOL = +29.625dB External resistor of Pre-Amp is "Rf = 10k, Ri = 680". (Refer to Figure 12) Note 18. Input from INTL, INTR, EXTL or EXTR pins. Pre-Amp Gain = + 23.9dB, PRE = "1", IVOL = +0dB External resistor of Pre-Amp is "Rf = 10k, Ri = 680". (Refer to Figure 12) 1.4 1.6 1.8 3 V mA 70 +18 3 100 +24 130 -4.5 +30 30 10 k dBV dB k pF min typ Max Units
* 0dBV = 1Vrms = 2.83Vpp
MS0140-E-01 -7-
2002/07
ASAHI KASEI
[AK4564]
(Continue) Parameter min typ max DAC Analog Output characteristics: Measured via LOUT1/ROUT1, LOUT2/ROUT2, VOL=+6.5dB Resolution S/(N+D) (0dBFS) DR (-60dBFS, A-Weighted) S/N (A-Weighted) Output Voltage (Note 19) Interchannel Isolation Interchannel Gain Mismatch Load Resistance Load Capacitance (Note 13) Headphone-Amp Characteristics: DAC a HPL/HPR pin Output Voltage (Note 20) HVDD = 3V (Note 21) HVDD = 4.5V S/(N+D) (Note 20) HVDD = 3V (Note 21) HVDD = 4.5V Output Noise Voltage (A-Weighted); HPG="0", HVDD=3V, RL=32 HPG="1", HVDD=4.5V, RL=100 Interchannel Isolation; HPG="0", HVDD=3V, RL=32 HPG="1", HVDD=4.5V, RL=100 Interchannel Gain Mismatch; HPG="0", HVDD=3V, RL=32 HPG="1", HVDD=4.5V, RL=100 Load Resistance; HVDD=2.63.6V, HPG = "0" HVDD=4.05.5V, HPG = "1" Load Capacitance (C1 in Figure 2) (C2 in Figure 2) -5.5 -1.1 50 50 -4.7 -0.3 70 66 -92 -77 80 80 -3.9 +0.5 dBV dBV dB dB dBV dBV dB dB dB dB pF nF 16 76 82 82 +1.2 80 10 30 82 88 88 +2 100 Units bits dB dB dB dBV dB dB k pF
+2.8 0.5
-86 -71
60 60
0.5 0.5 22 100 30 6.8
Speaker-Amp Characteristics: RL = 8, BTL, MIN a SP0/SP1, ALC2 = OFF Output Voltage (-6.5dBV Input) -4 -2 0 dBV S/(N+D) (-2dBV Output) 30 60 dB S/N (A-Weighted) 81 89 dB Load Resistance 8 Load Capacitance 10 pF Note 19. Output voltages are proportional to AVDD voltage. LOUT1, ROUT1, LOUT2, ROUT2 = (1.27 x AVDD) Vpp @VOL = +6.5dB Note 20. When DAC = 0dBFS Output, OATT = 0dB, HPG = "0", RL = 32, the output voltage is (0.59 x AVDD) Vpp. Note 21. When DAC = -12dBFS Output, OATT = 0dB, HPG = "1", RL = 100, the output voltage is (0.98 x AVDD) Vpp. HP-Amp
HPL, HPR 16
+
0.1 10
+
C1 C2 16
Oscillation prevention circuit
Figure 2. Headphone-Amp Output Circuit
* 0dBV = 1Vrms = 2.83Vpp
MS0140-E-01 -82002/07
ASAHI KASEI
[AK4564]
(Continue) Parameter Monaural Input: (MIN pin) Maximum Input Voltage (Note 22) Input Resistance Monaural Output: DAC a MIX a MOUT pin Output Voltage (Note 23) Load Resistance Load Capacitance (Note 13) BEEP1 Input: BEEP1 pin Maximum Output Voltage of Internal Amplifier (Note 24) Feed-back Resistance BEEP2 Input: BEEP2 pin Maximum Output Voltage of Internal Amplifier (Note 24) Feed-back Resistance Power Supply Current Power Up (PDN = "H") All Circuit Power-Up: (MIC=ADC=DAC=VCOM=HPP=SPKP=AOUTP1=AOUTP2= "1") AVDD+DVDD 13 MVDD (Note 25) 4.5 HVDD: HP-Amp Normal operation 6.5 (AOUTP2,1 = "1", HP-Amp No output) SVDD: SPK-Amp Normal operation 6.5 (SPPS= "1", SPK-Amp No output) ADC: (ADC=VCOM= "1") (Note 26) AVDD+DVDD DAC+LINEOUT: (DAC=AOUTP1=AOUTP2=VCOM= "1") AVDD+DVDD HVDD: LINEOUT Normal operation, HP-Amp Power OFF (AOUT1,2= "1", HPP = "0") Power Down (PDN= "L") AVDD+DVDD+HVDD+MVDD+SVDD (Note 27) 200 A Note 22. Maximum input voltage is proportional to AVDD voltage. (0.6 x AVDD) Vpp Note 23. DAC 0dBFS Output (Both L/R channels and the same phase) and OATT = 0dB. Note 24. Maximum output voltage is proportional to AVDD voltage. (0.6 x AVDD) Vpp Note 25. MPWR pin supplies 0mA. Note 26. As VCOM bit = "1", power supply current of HVDD is 0.8mA (typ.). Note 27. In power-down, all digital input pins including clock (MCLK, BCLK and LRCK) pins are held at "DVDD" or "DVSS". PDN pin is held at "DVSS". 7.5 5.5 2.5 19.5 6.8 9.8 9.8 mA mA mA mA 14 20 -4.5 26 dBV k 14 20 -4.5 26 dBV k -5.3 10 -4.5 -3.7 30 dBV k pF 14 23 -4.5 33 dBV k min typ max Units
-
mA mA mA
* 0dBV = 1Vrms = 2.83Vpp
MS0140-E-01 -9-
2002/07
ASAHI KASEI
[AK4564]
FILTER CHARACTERISTICS
(Ta=25C; AVDD, DVDD, SVDD=2.6 3.6V, MVDD, HVDD=2.6 5.5V; fs=48kHz; De-emphasis = OFF, Digital EQ/HPF/LPF = OFF) Parameter Symbol min typ max Units ADC Digital Filter (LPF): Passband (Note 28) 0.1dB PB 0 18.9 kHz -1.0dB 21.8 kHz -3.0dB 23.0 kHz Stopband (Note 28) SB 29.4 kHz Passband Ripple PR dB 0.1 Stopband Attenuation SA 65 dB Group Delay (Note 29) GD 19.0 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): Frequency Response (Note 28) -3.0dB FR 3.7 Hz -0.56dB 10 Hz -0.15dB 20 Hz DAC Digital Filter: Passband (Note 28) 0.1dB PB 0 21.7 kHz -6.0dB 24.0 kHz Stopband (Note 28) SB 26.2 kHz Passband Ripple PR dB 0.06 Stopband Attenuation SA 43 dB Group Delay (Note 29) GD 15.8 1/fs DAC Digital Filter + Analog Filter: (Note 30) FR dB 0.5 Frequency Response 0 20.0kHz Note 28. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.1dB). Note 29. The calculated delay time caused by digital filtering. This time is from the input of an analog signal to setting the 16bit data of both channels to the output register of the ADC and includes the group delay of the HPF. For DAC, this time is from setting the 16bit data of both channels on input register to the output of analog signal. Note 30. DAC a LOUT1/ROUT1, LOUT2/ROUT2
MS0140-E-01 - 10 -
2002/07
ASAHI KASEI
[AK4564]
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD, SVDD=2.6 3.6V, MVDD, HVDD=2.6 5.5V) Parameter Symbol min High-Level Input Voltage VIH 1.5 Low-Level Input Voltage VIL High-Level Output Voltage Iout=-200A VOH DVDD-0.2 Low-Level Output Voltage Iout=200A VOL Input Leakage Current Iin typ max 0.6 0.2 10 Units V V V V A
SWITCHING CHRACTERISTICS
(Ta=25C; AVDD, DVDD, SVDD=2.6 3.6V, MVDD, HVDD=2.6 5.5V; CL=20pF) Parameter Symbol min typ Master Clock Timing (MCLK) 256fs: Frequency fCLK 2.048 12.288 Pulse Width Low tCLKL 28 Pulse Width High tCLKH 28 384fs: Frequency fCLK 3.072 18.432 Pulse Width Low tCLKL 23 Pulse Width High tCLKH 23 LRCK Timing Frequency fs 8 48 Duty Cycle Duty 45 50 Audio Interface Timing BCLK Period tBLK 312.5 BCLK Pulse Width Low tBLKL 130 Pulse Width High tBLKH 130 LRCK Edge to BCLK "" (Note 31) tLRB 50 BCLK "" to LRCK Edge (Note 31) tBLR 50 LRCK to SDTO (MSB) Delay Time tLRM BCLK "" to SDTO Delay Time tBSD SDTI Latch Hold Time tSDH 50 SDTI Latch Set up Time tSDS 50 Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Latch Set up Time tCDS 50 CDTI Latch Hold Time tCDH 50 CSN "H" Time tCSW 150 CSN "" to CCLK "" tCSS 50 CCLK "" to CSN "" tCSH 50 Reset Timing PDN Pulse Width tPDW 150 PDN "" to SDTO Delay Time tPDV 4128 Note 31. BCLK rising edge must not occur at the same time as LRCK edge. max 12.8 Units MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1/fs
19.2
50 55
80 80
MS0140-E-01 - 11 -
2002/07
ASAHI KASEI
[AK4564]
n Timing Diagram
1/fCLK 1.5V 0.6V tCLKH 1/fs 1.5V 0.6V tBLK 1.5V 0.6V tBLKH tBLKL tCLKL
MCLK
LRCK
BCLK
Figure 3. Clock Timing 1.5V 0.6V tBLR tLRB 1.5V 0.6V tLRM tBSD D15 (MSB) tSDS D0 (LSB) tSDH 1.5V 0.6V 50%DVDD
LRCK
BCLK
SDTO
D14
SDTI
Figure 4. Audio Data Input/Output Timing (Audio I/F format: No. 0)
MS0140-E-01 - 12 -
2002/07
ASAHI KASEI
[AK4564]
CSN tCSS CCLK tCDS CDTI op2 0 op1 tCDH op0 A4 tCCKL tCCKH
1.5V 0.6V
1.5V 0.6V 1.5V 0.6V
Figure 5. WRITE Command Input Timing
tCSW CSN tCSH CCLK 1.5V 0.6V 1.5V 0.6V 1.5V 0.6V
CDTI
D3
D2
D1
D0
Figure 6. WRITE Data Input Timing
tPDW PDN 0.6V tPDV
SDTO
50%DVDD
Figure 7. Reset Timing
MS0140-E-01 - 13 -
2002/07
ASAHI KASEI
[AK4564]
OPERATION OVERVIEW
n System Clock The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs). The master clock (MCLK) should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be input as 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4564 may occur click noise. DAC input data should be "0" to avoid click noise. All external clocks (MCLK, BCLK and LRCK) should always be present except MIC = ADC = DAC = VCOM = HPP = SPKP = AOUT1P = AOUT2P = "0" or PDN = "L". If these clocks are not provided, the AK4564 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4564 should be placed in MIC = ADC = DAC = VCOM = HPP = SPKP = AOUT1P = AOUT2P = "0" or PDN = "L". However, ADC, DAC and ALC2 are in power-down mode until MCLK, BCLK and LRCK is input, even if they release a power-down mode by PDN pin or control register. (Refer to the "Power Management Mode".) n System Reset AK4564 should be reset once by bringing PDN pin "L" upon power-up. After the system reset operation, the all internal registers become initial value. Initializing cycle is 4128/fs=86ms@fs=48kHz. During initializing cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, "0". Output data of ADC settles data equivalent for analog input signal after initializing cycle. This cycle is not for DAC. n Digital High Pass Filter The AK4564 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC. The cut-off frequency of the HPF is 3.7Hz at fs=48kHz and it is attenuated to -0.15dB at 20Hz. This cut-off frequency scales with the sampling frequency (fs).
MS0140-E-01 - 14 -
2002/07
ASAHI KASEI
[AK4564]
n Audio Serial Interface Format
The SDTI, SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has four modes, MSB-first and 2's compliment. The data format is set by the DIF1-0 bits. SDTI is latched by "" of BCLK. SDTO is latched by "". When DIF1= "0" and DIF0="1", only BCLK=64fs is acceptable. No. 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO(ADC) SDTI(DAC) MSB justified LSB justified LSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 1. Audio Data Format BCLK 32fs = 64fs 32fs 32fs Figure Figure 8 Figure 9 Figure 10 Figure 11
RESET
LRCK
0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1
BCLK(32fs) SDTO(o) SDTI(i)
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15
1
BCLK(64fs) SDTO(o) SDTI(i)
15 14 13 13 2 1 0 15 14 13 1 2 1 0 15
Don't Care 15:MSB, 0:LSB Lch Data
15 14
1
0
Don't Care Rch Data
15 14
1
0
Figure 8. Audio Data Timing (No.0)
LRCK
0 1 2 15 16 17 18 19 20 31 0 1 2 15 16 17 18 19 20 31 0 1
BCLK(64fs) SDTO(o) SDTI(i)
15 15 14 13 12 4 1 0 15 15 14 13 12 1 0 15
Don't Care 15:MSB, 0:LSB
15 14 13 12
1
0
Don't Care
15 14 13 12
1
0
Lch Data
Rch Data
Figure 9. Audio Data Timing (No.1)
MS0140-E-01 - 15 -
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ASAHI KASEI
[AK4564]
LRCK
0 1 2 8 9 10 11 12 13 14 15 0 1 2 8 9 10 11 12 13 14 15 0 1
BCLK(32fs) SDTO(o) SDTI(I)
0
15 14
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14
1 2 3
8
14
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15
1
BCLK(64fs) SDTO(o) SDTI(i)
15 14 13 13 2 1 0 15 14 13 14 2 1 0 15
15 14 13
13 2
1
0
Don't Care
15 14 13 14
2
1
0
Don't Care
15
15:MSB, 0:LSB Lch Data Rch Data
Figure 10. Audio Data Timing (No.2)
LRCK
0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1
BCLK(32fs) SDTO(o) SDTI(I)
0
0
1
15
2
14 13
3 4
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
15 14 13
2 3 44
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
BCLK(64fs) SDTO(o) SDTI(i)
15 14 13 2 1 0 15 14 13 2 2 1 0
15 14 13
2
1
0
Don't Care
15 14 13
2
2
1
0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Audio Data Timing (No.3)
MS0140-E-01 - 16 -
2002/07
ASAHI KASEI
[AK4564]
n MIC BLOCK 1. Pre- Amp Pre-Amp includes selector, Internal MIC or External MIC Mode can be selected by INT/EXT bit. The Pre-Amp is non-inverting amplifier and internally biased to VCOM voltage with 100k (typ.). Gain (1+Rf/Ri) of the Pre-Amp is adjusted by external resistors and should be a range of +18 +30dB. An external capacitor is needed to cancel DC gain. The Cut-off frequency is determined by an external resistor (Ri) and a capacitor (C1). A capacitor of 100pF (C2) should be connected to prevent oscillation of Pre-Amp.
100pF(C2) C1
+
Ri
Rf
INT EXT
+
Pre-Amp
Figure 12. Pre-Amp 2. Power Supply for MIC The Power Supply for microphone device is supplied from MPWR pin. MPWR pin can supply the current up to 3mA. When the output current is 0mA, the output voltage is typically (MVDD - 1.2) V at MVDD=2.8V and typically (MVDD - 1.4) V at MVDD=4.5V. When the output current is 3mA, the output voltage is typically (MVDD - 1.5) V at MVDD=2.8V and typically (MVDD - 1.7) V at MVDD=4.5V. When MIC bit is "0", the output current is not supplied.
MS0140-E-01 - 17 -
2002/07
ASAHI KASEI
[AK4564]
n Analog Mixing Circuit for Recording Block
typ.20k To Rch MIX1 Ri BEEP1
+
BEEP1Amp
typ.100k typ.100k
BEEP1 AIN1, AIN2 or BEEP1
6.2k LIN1 (RIN1) 6.2k 6.2k 6.2k
typ.100k
AIN1
+
MIX1
AIN2 PRE
+
MIX2
To ADC
LIN2 (RIN2)
typ.100k
From Pre-Amp
To HP-Amp
Figure 13. Analog Mixing Circuit for Recording Block 1. BEEP1 Input When BEEP1 bit is "1", the input signal via BEEP1 pin can be applied to ADC. This signal level can be adjusted by an external resistor (Ri). Feed-back resistor of BEEP1-Amp is 20k 30% . (Refer to Figure 13) 2. LINE Input Input resistance of LIN1, RIN1, LIN2 and RIN2 are typically 100k and centered around the VCOM voltage. When the input voltage exceeds +2dBV, the input signals should be attenuated down to -4.3dBV at VA=2.8V by external resistor divider. When AIN1 bit is "1", LIN1 and RIN1 pins are selected. When AIN2 bit is "1", LIN2 and RIN2 pins are selected. If AIN1 and AIN2 bits are selected at the both input signals are mixed by the ratio of "1:1" 3. MIX1-Amp MIX1-Amp is powered-up when ADC bit = "1" or MIX1P bit = "0". 4. MIX2-Amp MIX2-Amp mixes Pre-Amp output and MIX1-Amp output at the ratio of "1:1".
MS0140-E-01 - 18 -
2002/07
ASAHI KASEI
[AK4564]
5. Polarity Input signals from INTL/INTR, EXTL/EXTR and BEEP1 pins are inverted and are output from ADC. Input signals from LIN1/RIN1 and LIN2/RIN2 pins are non-inverted and output from ADC. Signal Path Polarity INTL/INTR a ADC Inverted EXTL/EXTR a ADC Inverted BEEP1 a ADC Inverted LIN1/RIN1 a ADC Non-inverted LIN2/RIN2 a ADC Non-inverted Table 2. Polarity of Recording Block 6. MONO Mode When MONO bit is "1", the recording blocks in the AK4564 becomes MONO mode. The Pre-Amp, MIX1-Amp, MIX2-Amp and ADC analog block of the right channel are powered-down. And the right channel data of ADC is the same as the left channel data of ADC. When changing MONO mode, the ADC should be powered-up by changing ADC bit = "1" after MONO bit is changed to "1". Because click noise may occur when MONO bit is changed during ADC normal operation. n BEEP2 Input When BEEP2H bit is "1", the input signal from BEEP2 pin is output to Headphone-Amp. When BEEP2S bit is "1", the input signal from BEEP2 pin is output to Speaker-Amp. This signal level can be adjusted by an external resistor (Ri). An internal resistor value (Rf) is 20k 30% . In Speaker-Amp, the signal level is gained to +4.6dB internally.
Rf = 20k Ri BEEP2
+
Figure 14. Block diagram of BEEP2 inputs n MUTE Function When MUTE pin is "H", the output signals of LINEOUT, Headphone and Speaker-Amp are muted, and become VCOM or HVCM voltage. The switches of AOUT1, AOUT2, HPDAC, HPMIX, BEEP2H, ALCS and BEEP2S become "OFF" at the same time.
MS0140-E-01 - 19 -
2002/07
ASAHI KASEI
[AK4564]
n Output Digital Volume (OATT)
Attenuation range of the output digital volume is 0dB to -65.25dB with MUTE, and the step width is 0.75dB. When ZEC bit is "1", the attenuation level is changed by zero crossing detection or zero crossing timeout operation. Zero crossing timeout period is set by TM1-0 bits and FSTM bit. When ZCE is "0", it is changed immediately without zero crossing detection. Channel independent zero crossing detection is used. If new value is written to the OATT register before OATT changes by zero crossing or timeout, the previous value becomes invalid. When the OATT register is written continually, it should take an interval of zero crossing timeout and over. n LINEOUT LINEOUT signals are output from LOUT1/ROUT1 and LOUT2/ROUT2 pins. The output gain is set by VOL1 and VOL2 bits. The common voltage of these outputs is HVCM voltage and load resistance is min. 10k. The Power supply voltage for LINEOUT-Amp is supplied from HVDD pin. The output level of LINEOUT is constant regardless of HVDD voltage. When the voltage of HVDD pin is low, the distortion of LINEOUT degrades. When LINEOUTs are muted by AOUT1 or AOUT2 bit, the outputs become HVCM voltage and the amps go to Power-Save-Mode. When AOUTP1 (AOUTP2) bit is "0", LINEOUT-Amps become Power-Down-Mode and the output signal goes to Hi-Z. When PDN pin changes from "L" to "H" after power-up, LINEOUT-Amps become Power-Save-Mode. In Power-Save-Mode, LOUT1/ROUT1 (LOUT2/ROUT2) pins gradually become HVCM voltage via an internal resistor (typ.200k) from Hi-Z to decrease a pop noise. When Power OFF, the pop noise can be decreased by using Power-Save-Mode.
MS0140-E-01 - 20 -
2002/07
ASAHI KASEI
[AK4564]
n Headphone-Amps The Power supply voltage for Headphone-Amp is supplied from HVDD pin and centered around HVCM voltage. The load resistance and output voltage are specified by HVDD voltage. The output voltage can be changed by supplying AVDD voltage and HPG bit. (Refer to Table 3) HVDD 2.6 3.6V 4.0 5.5V HPG bit 0 1 Output Voltage (0.59 x AVDD) Vpp (0.98 x AVDD) Vpp Load Resistance (min) 22 100 Table 3. Load resistance and output voltage of Headphone-Amp When HPG bit is "0", the signals from MIX1, DAC and BEEP2 are output from Headphone-Amps with 0dB gain. When HPG is "1", the signals from MIX1, DAC and BEEP2 output from Headphone-Amps with +16.5dB gain. (Refer to Figure 15) When HPDAC, HPMIX and BEEP2H bits are "0", the input signals to Headphone-Amp are disabled and HPL/HPR pins output HVCM voltage. HPMIX, HPDAC and BEEP2H bits control ON/OFF of each input signal. When these bits are "1" at the same time, all input signals are mixed by the ration of "1:1". (Refer to Figure 13 and Figure 16)
+12dBV
+10dBV
+1.5dBV OATT = 0dB -4.5dBV -4.5dBV 0dBV
0dBV
FS
-10.5dBV -15dBV
-10dBV
FS-12dB
-16.5dBV
-16.5dBV
-20dBV
OATT=-10.5dB -27dBV
-30dBV
OATT+DAC
HP-AMP (+16.5dB)
Figure 15. Headphone-Amp Level Diagram (AVDD=2.8V, HVDD=4.5V, HPG = "1", OATT = 0dB& -10.5dB) * FS = Full Scale
MS0140-E-01 - 21 -
2002/07
ASAHI KASEI
[AK4564]
Headphone-Amps are powered-up/down by HPP bit. When HPP bit is "0", Headphone-Amps are powered-down and HPL and HPR pins are fixed to "L" (AVSS). At power-up/down, the common voltage of HPL/HPR pin is settled by a constant which determined by the internal resistor and the external capacitors. The internal resistor is 50k(typ) at power-up, and 1k(typ) at power-down. (Refer to Figure 16) Rising Time of Headphone-Amp: 1 = 50k x C1 Falling Time of Headphone-Amp: 2= 1k x (C1 + 2 x C2) For example; C1 = 4.7F, C2 = 100F 1 = 235ms 2 = 205ms
HPMIX bit From MIX1 HPDAC bit From DAC BEEP2H bit From BEEP2
HP-Amp
HPL, HPR 16 C2
+
+
MUTET 16
+
C1
Figure 16. Headphone-Amp internal equivalent circuit
HPP bit
HPDAC, HPMIX or BEEP2H bit 2 HPL/HPR pin 1 (1) (2) (3) (4)
Figure 17. Headphone-Amp Power-Up/Down Timing (1) Power-up Headphone-Amps: WR (HPP= "1") The common voltage of HPL/HPR pins rises by the time constant. (1) (2) Enable Headphone-Amp inputs: WR (HPDAC, HPMIX or BEEP2H ="1") The input signals from MIX1, DAC and BEEP2 are output. Headphone-Amps can output the signals while the common voltage is rising. (3) Disable Headphone-Amp inputs: WR (HPDAC=HPMIX=BEEP2H="0") The input signal from MIX1, DAC and BEEP2 are muted. Headphone-Amps output HVCM voltage during muting. (4) Power-down Headphone-Amps: WR (HPP="0") The common voltage of HPL/HPR pins falls by the time constant. (2)
MS0140-E-01 - 22 -
2002/07
ASAHI KASEI
[AK4564]
Headphone-Amps of the AK4564 has a possibility of oscillation depending on headphone characteristics. Therefore, Headphone-amp oscillation prevention circuit may be needed. Headphone-Amps oscillation prevention circuit example is shown in Figure 18. HP-Amp
HPL, HPR 16
+
0.1 10
+
16
Headphone Oscillation prevention circuit
Figure 18. Headphone-Amp oscillation prevention circuit example * When Headphone-Amp and Speaker-Amp are powered-up at the same time, refer to the condition of "Note 7", "Note 8" and "Note 10".
MS0140-E-01 - 23 -
2002/07
ASAHI KASEI
[AK4564]
n SPEAKER BLOCK The output signal from DAC is converted into a mono signal, [(L+R)/2], and is supplied to Speaker-Amp via ALC2 circuit. This Speaker-Amp has a monaural output by BTL, which can be output up to 80mW at 8. Speaker Blocks (MOUT, ALC2 and Speaker-Amp) can be powered-up/down by SPKP bit. When SPKP bit is "0", MOUT, SP0 and SP1 pins go Hi-Z. When SPPS bit is "0" and SPKP bit is "1", Speaker-Amp becomes Power-Save-Mode. Then SP0 pin goes Hi-Z and SP1 pin is output to SVDD/2 via 100k (typ.). When PDN pin changes from "L" to "H" after power-up, Speaker-Amp goes to Power-Save-Mode. In Power-Save-Mode, SP1 pin gradually become HVCM voltage via an internal resistor (typ.200k) from Hi-Z to decrease a pop noise. When Power-down (SPKP = "0"), the pop noise can be decreased by controlling via Power-Save-Mode. * When Headphone-Amp and Speaker-Amp are powered-up at the same time, refer to the condition of "Note 7", "Note 8" and "Note 10". 1. Mono Output MOUT pin outputs analog mixed signal, [(L+R)/2] of DAC output. When MOUT bit is "0", this output is disabled and MOUT pin goes to VCOM voltage. The load impedance is 10k (min.). When SPKP bit is "0", MOUT pin becomes Power-Down-Mode and outputs Hi-Z. 2. ALC2 The input resistance of ALC2 is 23k (typ.) and centered around VCOM voltage. The level diagram of ALC2 operation is shown in Figure 19 ALC2 limiter detection level is -6.5dBV regardless of power supply voltage. When the input signal level exceeds -6.5dBV (=FS-2dB@AVDD=2.8V), the output level of ALC2 is limited. When the signal over -6.5dBV and is input continuously to the ALC2 circuit, the changing period of ALC2 limiter operation is 2/fs=42s@fs=48kHz and the output level is attenuated by 0.5dB/step. The ALC2 recovery operation is done by zero crossing detection and the output is gained by 1dB/step. The ALC2 recovery operation is done until the output level of Speaker-Amp goes to -8.5dBV(=FS-4dB@AVDD=2.8V). The ALC2 recovery operation period is fixed to 2048/fs=42.7mS@fs=48kHz. When inputting signal between -6.5dBV and -8.5dBV, both the limiter and recovery operations of ALC2 are not done. When PDN pin changes from "L" to "H" or SPKP bit changes from "0" to "1", the initilizing cycle (2048/fs = 42.7ms @fs=48kHz) starts. ALC2 is disabled during initilizing cycle, ALC2 starts after finishing the initilizing cycle. Parameter Operation Start Level Period fs=48kHz fs=32kHz ALC2 Limiter operation -6.5dBV 2/fs = 42s 2/fs = 63s No 0.5dB step Table 4. Content of ALC2 ALC2 Recovery operation -8.5dBV 2048/fs = 42.7ms 2048/fs = 64ms Yes(Timeout = 2048/fs ) 1dB step
Zero Crossing Detection ATT/GAIN
MS0140-E-01 - 24 -
2002/07
ASAHI KASEI
[AK4564]
FS-2dB = -6.5dBV
+4.6dB -1.9dBV
0dBV
Full-differential
FS
-4.5dBV
-4.5dBV
-2dB +6dB -7.9dBV
OATT = 0dB -12.75dBV
Single-ended
-10dBV
+9.75dB -1.4dB FS-4dB = -8.5dBV +18dB
FS-12dB
-16.5dBV
-16.5dBV
-20dBV
OATT = -8.25dB -24.75dBV
-30dBV
OATT+DAC
ALC2 SPK-AMP
Figure 19. Speaker-Amp Output Level Diagram (AVDD=2.8V, OATT= -8.25dB & 0dB) *FS = Full Scale
BEEP2S bit From BEEP2 ALCS bit From ALC2
+
SP1
+
Figure 20. Speaker-Amp Internal equivalent circuit
SP0
8
MS0140-E-01 - 25 -
2002/07
ASAHI KASEI
[AK4564]
n Digital EQ/HPF/LPF Circuits
The AK4564 performs equalizing, filtering and ALC (Automatic Level Control) by digital domain for A/D converter data. The equalizing circuit emphasizes stereo separation when using internal microphone. LPF1, LPF2 and HPF2 are IIR filters of 1st order to compensate frequency response of microphone and etc. HPF3 is IIR filter of 2nd order to cut a wind-noise. Refer to the section of "ALC1 operation" about ALC1.
MIX
Main Lch HPF3 LPF1 LPF2 HPF2 Sub HPF1
+
ALC1
Lch
HPF1 Sub Rch HPF3 LPF1 LPF2 HPF2 Main wind-noise cut Filtering Equalizing
+
MIX
ALC1
Rch
Figure 21. Digital EQ/HPF/LPF
MS0140-E-01 - 26 -
2002/07
ASAHI KASEI
[AK4564]
n ALC1 Operation
1. ALC1 Limiter Operation When the ALC1 limiter is enabled and either Lch or Rch exceed the ALC1 limiter detection level (LMTH1-0), the IVOL value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0) automatically. The operation is done at the zero crossing points of the waveform. And the timeout period of the zero crossing detection is set by ZTM1-0 bits. The IVOL value is common between L/R channels. After finishing the operation for attenuation, if ALC1 bit is set to "0", the operation of attenuation repeats when the input signal level exceed the ALC1 limiter detection level (LMTH1-0). 2. ALC1 Recovery Operation After completing an ALC1 limiter operation, the ALC1 recovery operation waits a time defined in WTM1-0 bits. If the input signal does not exceed the "ALC1 recovery waiting counter reset level (LMTH1-0)" during the waiting time, the ALC1 recovery operation starts. The IVOL value increases automatically up to the set reference level (REF7-0 bits) during this operation. The IVOL value is common between L/R channels. The ALC1 recovery operation is done at a period set by WTM1-0 bits. If the zero crossing operation of both L/R channels is completed during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and then the next recovery operation starts. When "ALC1 recovery waiting counter reset level (LMTH1-0) Output Signal < ALC1 limiter detection level (LMTH1-0)" during the ALC1 recovery operation, the waiting timer of ALC1 recovery operation is reset. When "ALC1 recovery waiting counter reset level (LMTH1-0) > Output Signal", the waiting timer of ALC1 recovery operation starts. When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by FR bit = "1". n Writing to IVOL register when ALC1 is OFF When writing control register continuously, the change of IVOL should be written after zero crossing timeout. If IVOL is changed by writing to control register before zero crossing detection, IVOL value of L/R channels may not give a difference level.
MS0140-E-01 - 27 -
2002/07
ASAHI KASEI
[AK4564]
The following registers should not be changed during the ALC1 operation. WTM1-0, ZTM1-0, LMTH1-0, LMAT1-0, RGAIN1-0, REF7-0, FR
Manual Mode
WR (Power Management Control & Signal Select registers)
WR (ZTM1-0, WTM1-0)
WR (LMAT1-0, RGAIN1-0, LMTH1-0)
WR (REF7-0)
WR (IVOL7-0)
*1: The value of IVOL should be the same or smaller than REF's
WR (ALC1= "1")
ALC1 Operation
No
Finish ALC1 mode?
Yes WR (ALC1= "0") *2 Finish ALC1 mode and return to manual mode
Figure 22. Registers set-up sequence at ALC1 operation *2: When ALC1 bit changes into "0", it takes a period set by ZTM1-0 bit to return manual mode.
MS0140-E-01 - 28 -
2002/07
ASAHI KASEI
[AK4564]
n FADEIN Mode In FADEIN Mode, the IVOL value increase gradually by the step set by FDATT1-0 bits when FDIN bit changes from "0" to "1". The FADEIN period is set by FSTM, REF7-0, FDATT1-0 and FDTM1-0 bits. The FADEIN operation is done by the zero crossing detection. The operation stops when the IVOL value becomes the REF value or the limiter detection level (LMTH). If the limiter operation is done during FADAIN period, the FADEIN operation stops and the ALC1 operation starts. NOTE: When FDIN and FDOUT bits are set to "1" at the same time, FADEOUT operation is prior to FADEIN operation.
SDTO Output
ALC1 bit FDIN bit
(5)
(1) (2)
(3)
(4)
Figure 23. Example for controlling sequence in FADEIN operation (1) WR (ALC1 = FDIN = "0"): The ALC1 operation is disabled. To start the FADEIN operation, FDIN bit is written in "0". (2) WR (IVOL = "00H"): IVOL output is muted. The writing to IVOL should wait a zero crossing timeout period set by ZTM1-0 bits. (3) WR (ALC1 = FDIN = "1"): The FADEIN operation starts. The IVOL is fade-in from MUTE state. (4) The FADEIN operation is done until the limiter detection level (LMTH1-0) or the reference level (REF7-0). After completing the FADEIN operation. The FADEIN operation is completed and the ALC1 operation starts. (5) FADEIN time is set by REF7-0, FDTM1-0, FSTM and FDATT bits e.g. REF7-0 = E1H(225 dec), FDTM1-0 = 40ms, FDATT1-0 = 2 step (225 x FDTM1-0) / FDATT1-0 = 225 x 40ms /2 = 4.5s
MS0140-E-01 - 29 -
2002/07
ASAHI KASEI
[AK4564]
n FADEOUT Mode In FADEOUT mode, the present IVOL value decreases gradually down to the MUTE state when FDOUT bit changes from "0" to "1". The operation is done by the zero crossing detection. If the large signal is supplied to the ALC1 circuit during the FADEOUT operation, the ALC1 limiter operation starts. However, the total time of the FADEOUT operation is the same time, even if the limiter operation is done. The period of FADEOUT is set by FSTM and FDTM1-0 bits, the number of step is set by FDATT1-0 bits. When FDOUT bit changes into "0" during the FADEOUT operation, the ALC1 operation starts from the present IVOL value. When FDOUT and ALC1 bits change into "0" at the same time, the FADEOUT operation stops and the IVOL keeps the value at that time. NOTE: When FDIN and FDOUT bits are set to "1" at the same time, FADEOUT operation is prior to FADEIN operation.
SDTO Output
ALC1 bit FDOUT bit
(2) (1) (3) (4) (5) (6) (7) (8)
Figure 24. Example for controlling sequence in FADEOUT operation (1) WR (FDOUT = "1"): The FADEOUT operation starts. Then ALC1 bit should be always "1". (2) FADEOUT time is set by REF7-0, FDTM1-0 and FDATT bits. e.g. REF7-0 = E1H(225 dec), FDTM1-0 = 40ms, FDATT1-0 = 2 step (225 x FDTM1-0) / FDATT1-0 = 225 x 40ms / 2 = 4.5s (3) The FADEOUT operation is completed. The IVOL value is the MUTE state. If FDOUT bit keeps "1", the IVOL value keeps the MUTE state. (4) Analog and digital outputs are muted externally. Then the IVOL value is the MUTE state. (5) WR (ALC1 = FDOUT = "0"): Exit the ALC1 and FADEOUT operations (6) WR (IVOL = XXH): The IVOL value should be set to the same or smaller than REF's. (7) WR (ALC1 = "1", FDOUT = "0"): The ALC1 operation restarts. But the ALC1 bit should be written until completing zero crossing detection operation of IVOL. (8) Release an external mute function for analog and digital outputs.
MS0140-E-01 - 30 -
2002/07
ASAHI KASEI
[AK4564]
n Control Register WRITE Timing The data on the 3 wires serial interface consists of op-code (3bit), address (MSB-first, 5bit) and control data (MSB-first, 8bit). The transmitting data is output to each bit by "" of CCLK, the receiving data is latched by "" of CCLK. Writing data becomes effective by "" of CSN. CCLK always needs 16 edges of "" during CSN = "L". PDN pin = "L" resets the registers to their defalut values.Only write to address 00H to 0CH. Writing to the control registers except for op2-0 bit ="101" are ignored.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
op2 op1 op0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1"
op2-op0: Op code (101:WRITE) A4-A0: Register Address D7-D0: Control data
Figure 25. Control Data Timing
MS0140-E-01 - 31 -
2002/07
ASAHI KASEI
[AK4564]
n Register Map
The following registers are reset at PDN pin = "L". Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH D6 D5 D4 HPMIX HPG BEEP1 ALCS BEEP2H BEEP2S Power Management Control AOUTP2 AOUTP1 SPKP HPP Mode Control VOL2-1 VOL2-0 VOL1-1 VOL1-0 Filter Select 1 MIX1 MIX0 HPF3 HPF2-1 Filter Select 2 0 0 0 LPF2D Timer Select TM1 TM0 FDTM1 FDTM0 ALC Mode Control 1 0 GSEL FDATT1 FDATT0 0 ALC Mode Control 2 0 FSTM 0 ALC Mode Control 3 REF7 REF6 REF5 REF4 Input Digital Volume Control IVOL7 IVOL6 IVOL5 IVOL4 Operation Mode 0 0 MIX1P MONO Output Digital ATT Control ZCE OATT6 OATT5 OATT4 Table 5. AK4564 Register Map Register Name Signal Select 1 Signal Select 2 D7 0 SPPS D3 AIN2 AOUT2 VCOM DIF1 HPF2-0 LPF2-1 ZTM1 RGAIN1 0 REF3 IVOL3 ALC2 OATT3 D2 AIN1 AOUT1 DAC DIF0 HPF1-1 LPF2-0 ZTM0 RGAIN0 FR REF2 IVOL2 FDIN OATT2 D1 D0 PRE INT/EXT MOUT HPDAC ADC MIC DEM1 DEM0 HPF1-0 FSF LPF1-1 LPF1-0 WTM1 WTM0 LMAT1 LMAT0 LMTH1 LMTH0 REF1 REF0 IVOL1 IVOL0 FDOUT ALC1 OATT1 OATT0
Signal Select 1 Addr Register Name 00H Signal Select 1 Default
D7 0 0
D6 HPMIX 0
D5 HPG 0
D4 BEEP1 0
D3 AIN2 0
D2 AIN1 0
D1 PRE 1
D0 INT/EXT 0
INT/EXT: Select Internal / External MIC 0: Internal MIC (Default) 1: External MIC PRE: Enable input signal from Pre-Amp to ADC. 0: OFF (Default) 1: ON AIN1: Enable input signal from LIN1/RIN1 pin to ADC. 0: OFF (Default) 1: ON AIN2: Enable input signal from LIN2/RIN2 pin to ADC. 0: OFF (Default) 1: ON BEEP1: Enable input signal from BEEP1 pin to ADC. 0: OFF (Default) 1: ON HPG: Select gain of Headphone-Amp 0: 0dB (Default) 1: + 16.5dB HPMIX: Enable input signal from MIX1-Amp to Headphone-Amp 0: OFF (Default) 1: ON
MS0140-E-01 - 32 -
2002/07
ASAHI KASEI
[AK4564]
Signal Select 2 Addr Register Name 01H Signal Select 2 Default
D7 SPPS 0
D6 ALCS 0
D5 D4 D3 D2 BEEP2H BEEP2S AOUT2 AOUT1 0 0 0 0
D1 MOUT 0
D0 HPDAC 0
HPDAC: Enable input signal from Headphone-Amp to DAC output 0: OFF (Default) 1: ON MOUT: Enable mono output [Mixing = (L+R)/2]. 0: OFF (Default) 1: ON When MOUT bit = "0", MOUT pin outputs VCOM voltage. AOUT1: Enable LOUT1/ROUT1 output 0: OFF (Default) 1: ON When AOUT1 bit = "0", the outputs become HVCM voltage and the amps go to Power-Save-Mode. AOUT2: Enable LOUT2/ROUT2 output 0: OFF (Default) 1: ON When AOUT2 bit = "0", the outputs become HVCM voltage and the amps go to Power-Save-Mode. BEEP2S: Enable BEEP2 to Speaker-Amp 0: OFF (Default) 1: ON BEEP2H: Enable BEEP2 to Headphone-Amp 0: OFF (Default) 1: ON ALCS: Enable ALC2 to Speaker-Amp 0: OFF (Default) 1: ON SPPS: Speaker-Amp Power-Save-Mode 0: Power-Save-Mode (Default) 1: Normal operation When SPPS bit = "0", SP0 pin becomes Hi-Z and SP1 pin is generated to SVDD/2 voltage.
MS0140-E-01 - 33 -
2002/07
ASAHI KASEI
[AK4564]
Power Management Control Addr Register Name D7 D6 02H Power Management Control AOUT2P AOUT1P Default 1 1
D5 SPKP 1
D4 HPP 0
D3 VCOM 1
D2 DAC 1
D1 ADC 1
D0 MIC 1
MIC: MIC Block (Pre-Amp and MPWR) Power Control. 0: OFF 1: ON (Default) When MIC bit = "0", Output of Pre-Amp is Hi-Z and MPWR is terminated by 5k (typ) to MVSS. ADC: ADC Power Control 0: OFF 1: ON (Default) When ADC bit = "0", SDTO pin is fixed to "L". When ADC bit changes from "0" to "1", initializing cycle (4128/fs=86ms@fs=48kHz) starts. After initializing cycle, digital data of ADC is generated. DAC: DAC Power Control 0: OFF 1: ON (Default) VCOM: Common Voltage (VCOM and HVCM) Power Control 0: OFF 1: ON (Default) HPP: Headphone-Amp Power Control 0: OFF (Default) 1: ON When HPP bit = "0", output of Headphone-Amp becomes "L" (AVSS). SPKP: Speaker Block Power Control (Including BEEP2, MOUT, ALC2 and Speaker-Amp) 0: OFF 1: ON (Default) When SPKP bit = "0", output of Speaker-Amp and MOUT are Hi-Z. AOUT1P: LOUT1/ROUT1's Amplifiers Power Control 0: OFF 1: ON (Default) When AOUT1P bit = "0", LOUT1/ROUT1 pins are Hi-Z. AOUT2P: LOUT2/ROUT2's Amplifiers Power Control 0: OFF 1: ON (Default) When AOUT2P bit = "0", LOUT2/ROUT2 pins are Hi-Z. Each block can be partially powered-down by ON/OFF ("1" / "0") of these bits. When PDN pin goes "L", all circuits are powered-down regardless of these bits. However in this case, all register are reset to the default value. When all these registers in 02H goes "0", all circuits can be powered-down with keeping registers values. VCOM bit must go "1" before each block operates. Except the case of MIC=ADC=DAC=VCOM=HPP=SPKP=AOUT1P=AOUT2P = "0" or PDN pin = "L", MCLK, BCLK and LRCK should not be stopped.
MS0140-E-01 - 34 -
2002/07
ASAHI KASEI
[AK4564]
MIC MPWR D0:MIC
Input Selector *2 D1:ADC
ADC ALC1
VCOM HP HVCM D3:VCOM D4:HPP
DAC ATT D2:DAC BEEP2 AOUT2 AOUT1
MOUT SPK ALC2
D5:SPKP
*1
D7:AOUT2P
D6:AOUT1P
*1: BEEP2 is enabled by controlling SPKP or HPP bit. *2: MIX1-Amp is enabled by controlling ADC or DACMIX bit
Figure 26. Power Management Control
MIC MPWR MVDD
Input Selector AVDD
ADC ALC1
VCOM HP HVCM VCOM: AVDD HVDD HVCM: HVDD
DAC ATT AVDD BEEP2 AOUT2 AOUT1
SPK
MOUT ALC2 AVDD
SVDD
AVDD
HVDD
HVDD
Figure 27. Analog Power Supply Source of Each Block
MS0140-E-01 - 35 -
2002/07
ASAHI KASEI
[AK4564]
Mode Control Addr Register Name 03H Mode Control Default
D7 D6 D5 D4 VOL2-1 VOL2-0 VOL1-1 VOL1-0 0 1 0 1
D3 DIF1 0
D2 DIF0 0
D1 DEM1 0
D0 DEM0 1
DEM1-0: Select De-emphasis Frequency The AK4564 includes the digital de-emphasis filter (tc = 50/15s) by IIR filter. The filter corresponds to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 registers are enabled for input audio data. DEM1 DEM0 Mode Default
0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 6. De-emphasis Frequencies DIF1-0: Select Audio Data Format No. 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO(ADC) SDTI(DAC) MSB justified LSB justified LSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 7. Audio Data Format
BCLK 32fs = 64fs 32fs 32fs
Figure Figure 8 Figure 9 Figure 10 Figure 11
Default
VOL1: LOUT1/ROUT1 output volume setting VOL2: LOUT1/ROUT1 output volume setting The Power supply voltage for LINEOUT-Amp is supplied from HVDD pin. The output level of LINEOUT is constant regardless of HVDD voltage. When the output voltage of HVDD pin is low, the distortion of LINEOUT degrades. VOL2-1 VOL1-1 0 0 1 1 VOL2-0 VOL1-0 GAIN AVDD Voltage LINEOUT +2dBV +2dBV +2dBV -4.5dBV
0 +7.1dB 2.6V 1 +6.5dB 2.8V 0 +5.9dB 3.0V 1 0dB 2.8V Table 8. LINEOUT volume setting
Default
MS0140-E-01 - 36 -
2002/07
ASAHI KASEI
[AK4564]
Filter Select 1 Addr Register Name 04H Filter Select 1 Default
D7 MIX1 0
D6 MIX0 0
D5 HPF3 0
D4 HPF2-1 0
D3 HPF2-0 0
D2 HPF1-1 0
D1 HFP1-0 0
D0 FSF 0
FSF: Select sampling rate to match a coefficient of digital filter 0: fs = 48kHz (Default) 1: fs = 32kHz HPF1: Select cut-off frequency of HPF1 in EQ block. This is 1st order and IIR filter. HPF1-1 HPF1-0 Cut-off Frequency fs=32kHz fs=48kHz OFF 6kHz 7.5kHz 9kHz Default
0 0 OFF 0 1 6kHz 1 0 7.5kHz 1 1 9kHz Table 9. Select cut-off frequency of HPF1
HPF2: Select cut-off frequency of HPF2 to revise frequency response. This is 1st order and IIR filter. HPF2-1 HPF2-0 Cut-off Frequency fs=32kHz fs=48kHz Default
0 0 OFF OFF 0 1 100Hz 100Hz 1 0 200Hz 200Hz 1 1 300Hz 300Hz Table 10. Select cut-off frequency of HPF2
HPF3: Select cut-off frequency of HP3 for wind-noise cut. This is 2nd order and IIR filter. The cut-off frequency is fixed to 400Hz and is changed by FSF bit. 0: OFF (Default) 1: ON MIX1-0: Select Mixing value in EQ block. When HPF1 is OFF, this circuit is also OFF. MIX1 0 0 1 1 MIX0 Main : Sub Default
0 1: 1 1 1: 1.25 0 1: 0.5 1 1: 0.75 Table 11. Select Mixing value
MS0140-E-01 - 37 -
2002/07
ASAHI KASEI
[AK4564]
Filter Select 2 Addr Register Name 05H Filter Select 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 LPF2D 0
D3 LPF2-1 0
D2 LPF2-0 0
D1 LPF1-1 0
D0 LPF1-0 0
LPF1: Select cut-off frequency of LPF1 to revise frequency response. This is 1st order and IIR filter. LPF1-1 LPF1-0 Cut-off Frequency fs=32kHz fs=48kHz Default
0 0 OFF OFF 0 1 6kHz 6kHz 1 0 9kHz 9kHz 1 1 13.5kHz 13.5kHz Table 12. Select cut-off frequency of LPF1
LPF2: Select cut-off frequency of LPF2 to revise frequency response. This is 1st order and IIR filter. LPF2-1 LPF2-0 Cut-off Frequency fs=32kHz fs=48kHz Default
0 0 3kHz 3kHz 0 1 4.5kHz 4.5kHz 1 0 6.75kHz 6.75kHz 1 1 10.125kHz 10.125kHz Table 13. Select cut-off frequency of LPF2 LPF2D: Enable LPF2 0: OFF (Default) 1: LPF2 ON
MS0140-E-01 - 38 -
2002/07
ASAHI KASEI
[AK4564]
Timer Select Addr Register Name 06H Timer Select Default
D7 TM1 0
D6 TM0 1
D5 FDTM1 0
D4 FDTM0 1
D3 ZTM1 1
D2 ZTM0 0
D1 WTM1 1
D0 WTM0 0
WTM1-0: ALC1 Recovery Waiting Period A period of recovery operation when any limiter operation does not occur during ALC1 operation. WTM1 WTM0 ALC1 Recovery Period 0 0 6ms 0 1 24ms 1 0 48ms Default 1 1 96ms Table 14. ALC1 Recovery Operation Waiting Period ZTM1-0: IVOL Zero crossing Timeout Period When IVOL of each L/R channels do zero crossing or timeout independently, the IVOL value is changed by P WRITE operation or ALC1 recovery operation. ZTM1 ZTM0 Zero Crossing Timeout Period 0 0 6ms 0 1 24ms 1 0 48ms Default 1 1 96ms Table 15. Zero Crossing Timeout Period FDTM1-0: FADEIN/OUT Cycle Setting The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT bits are set to "1". When IVOL of each L/R channel do zero crossing or timeout independently, the IVOL value is changed. FDTM1 0 0 1 1 FDTM0 FADEIN/OUT Period 0 20ms 1 40ms 0 48ms 1 56ms Table 16. FADEIN/OUT Period
Default
TM1-0: Select zero crossing timeout period of OATT These bits are enabled at ZCE = "1". TM1 TM0 Zero Crossing Timeout Period 0 0 8ms 0 1 16ms 1 0 32ms 1 1 64ms Table 17. Select zero crossing timeout of OATT
Default
* WTM1-0, ZTM1-0, FDTM1-0 and TM1-0 have the same time between fs=32kHz (FSTM bit = "1") and fs=48kHz (FSTM bit = "0").
MS0140-E-01 - 39 -
2002/07
ASAHI KASEI
[AK4564]
ALC Mode Control 1 Addr Register Name 07H ALC Mode Control 1 Default
D7 0 0
D6 GSEL 0
D5
FDATT1
D4 0
D3 0
D2 0
D1 0
D0 LMAT0 0
FDATT0 RGAIN1 RGAIN0 LMAT1
0
LMAT1-0: ALC1 Limiter ATT Step The IVOL value is attenuated when the input signal exceeds the ALC1 limiter detection level. The number of step to attenuate is decided by output level. ALC1Limiter ATT Step LMAT1 0 0 1 1 LMAT0 0 1 0 1 ALC1 Output ALC1 Output LMTH FS ALC1 Output FS + 6dB 1 2 4 4 ALC1 Output FS + 12dB 1 2 4 8 Default
1 1 2 2 2 2 2 4 Table 18. ALC1 Limiter ATT Step
RGAIN1-0: ALC1 Recovery GAIN Step During the ALC1 recovery operation, the number of steps changed from current IVOL value is set. For example, when the current IVOL value is 30H, RGAIN1-0= "01" are set, IVOL changes to 32H by the auto limiter operation, the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL value does not increase. RGAIN1 RGAIN0 GAIN STEP Default
0 0 1 0 1 2 1 0 3 1 1 4 Table 19. ALC1 Recovery GAIN Step
FDATT1-0: FADEIN/OUT ATT Step Setting During the FADEIN/OUT operation, the number of steps changed from current IVOL value is set. FDATT1 FDATT0 ATT STEP
Default 0 0 1 0 1 2 1 0 3 1 1 4 Table 20. FADEIN/OUT ATT Step Setting GSEL: Select IVOL gain 0: MIC (Default) 1: LINE
MS0140-E-01 - 40 -
2002/07
ASAHI KASEI
[AK4564]
ALC Mode Control 2 Addr Register Name 08H ALC Mode Control 2 Default
D7 0 0
D6 FSTM 0
D5
0
D4 0 0
D3 0 0
D2 FR 1
D1 LMTH1 1
D0 LMTH0 0
0
LMTH1-0: ALC1 Limiter Detection Level / Recovery Counter Reset Level LMTH1 0 0 1 1 LMTH0 ALC1 Limier Detection Level ALC1 Recovery Waiting Counter Reset Level -2.5dBFS > ALC1 Output -4.1dBFS 0 ALC1 Output -2.5dBFS -4.1dBFS > ALC1 Output -6.0dBFS 1 ALC1 Output -4.1dBFS Default -6.0dBFS > ALC1 Output -8.5dBFS 0 ALC1 Output -6.0dBFS -8.5dBFS > ALC1 Output -12dBFS 1 ALC1 Output -8.5dBFS Table 21. ALC1 Limiter Detection Level / Recovery Counter Reset Level
FR: Enable ALC1 Fast Recovery Operation 0: Disable 1: Enable (Default) If the impulse noise is supplied, the ALC1 recovery operation becomes the faster period than a set of ZTM1-0 and WTM1-0 bits. FSTM: This data determines the time of ALC1 recovery period (WTM1-0 bit), IVOL zero crossing timeout period (ZTM1-0 bit), OATT zero crossing timeout period (TM1-0 bit) and FADEIN/OUT period (FDTM1-0 bit) 0: fs = 48kHz (Default) 1: fs = 32kHz
MS0140-E-01 - 41 -
2002/07
ASAHI KASEI
[AK4564]
ALC Mode Control 3 Addr Register Name 09H ALC Mode Control 3 Default
D7 REF7 1
D6 REF6 1
D5 REF5 1
D4 REF4 0
D3 REF3 0
D2 REF2 0
D1 REF1 0
D0 REF0 1
REF7-0: Reference value at ALC1 Recovery Operation. 0.375dB step, 242 Levels During the ALC1 recovery operation, if the REF value exceeds the setting reference value by Gain operation, REF value does not become larger than the reference value. GSEL bit selects the gain table of either MIC or LINE. GAIN(dB) MIC LINE (GSEL bit = "0") (GSEL bit = "1") F1H +36.0 +6.0 F0H +35.625 +5.625 EFH +35.25 +5.25 * * * E2H +30.375 +0.375 E1H +30.0 0 Default E0H +29.625 -0.375 DFH +29.25 -0.75 * * * 04H -52.875 -82.875 03H -53.25 -83.25 02H -53.625 -83.625 01H -54.0 -84.0 00H MUTE MUTE Table 22. Set-up Reference Level at ALC1 Recovery operation DATA
MS0140-E-01 - 42 -
2002/07
ASAHI KASEI
[AK4564]
Input Digital ATT Control Addr Register Name 0AH
Input Digital Volume Control
D7 IVOL7 1
D6 IVOL6 1
D5 IVOL5 1
D4 IVOL4 0
D3 IVOL3 0
D2 IVOL2 0
D1 IVOL1 0
D0 IVOL0 1
Default
IVOL7-0: Input Digital Volume; 0.375dB step, 242 Level When the ALC1 operation is OFF, IVOL can be used as volume. When the IVOL is changed, the IVOL is detected by zero crossing. Zero crossing timeout period is set by ZTM1-0 and FSTM bits. The change of gain table between MIC and LINE is set by GSEL bit. During the ALC1 operation, the writing value in IVOL7-0 bits is ignored GAIN(dB) LINE MIC (GSEL bit = "0") (GSEL bit = "1") F1H +36.0 +6.0 F0H +35.625 +5.625 EFH +35.25 +5.25 * * * E2H +30.375 +0.375 E1H +30.0 0 Default E0H +29.625 -0.375 DFH +29.25 -0.75 * * * 04H -52.875 -82.875 03H -53.25 -83.25 02H -53.625 -83.625 01H -54 -84 00H MUTE MUTE Table 23. Attenuation value of Input Digital Volume DATA
MS0140-E-01 - 43 -
2002/07
ASAHI KASEI
[AK4564]
Operation Mode Addr Register Name 0BH
D7
D6
D5
D4
D3
D2
D1
D0
Operation Mode 0 0 MIX1P MONO ALC2 FDIN FDOUT ALC1 Default 0 0 0 0 1 0 0 0 ALC1: ALC1 Enable Flag 0: Disable (Default) 1: Enable FDOUT: FADEOUT Enable Flag 0: Disable (Default) 1: Enable FDIN: FADEIN Enable Flag 0: Disable (Default) 1: Enable ALC2: ALC2 Enable Flag 0: Disable 1: Enable (Default) After initializing cycle (2048/fs=42.7ms@fs=48kHz), ALC2 is enabled. This initializing cycle starts when PDN pin change "L" to "H" or SPKP bit change from "0" to "1". MONO: MONO mode for Recoding When the microphone and line inputs are mono, Rch output data of SDTO can be changed to Lch data. Then Pre-Amp, MIX1-Amp, MIX2-Amp and ADC analog block of right channel are powered down. MONO 0 1 SDTO Output Data Lch Rch Mode Default
Lch Rch Stereo Mono Lch Lch Table 24. SDTO Output Data
MIX1P: MIX1-Amp Power Control MIX1P and ADC bits are Ored. 0: Power OFF (Default) 1: Power ON
MS0140-E-01 - 44 -
2002/07
ASAHI KASEI
[AK4564]
Output Digital ATT Control Addr Register Name 0CH
Output Digital ATT Control
D7 ZCE 1
D6 OATT6 1
D5 OATT5 0
D4 OATT4 1
D3 OATT3 1
D2 OATT2 0
D1 OATT1 0
D0 OATT0 0
Default
ZCE: OATT Zero Crossing Enable Flag 0: Disable 1: Enable (Default) OATT6-0: Output Digital Volume; 89 Level, 0dB ~ -65.25dB & Mute, 0.75dB step This volume includes zero crossing detection circuit. When ZCE is "1", the change of volume is detected by zero crossing independently. Zero crossing timeout period is set by TM1-0 and FSTM bits. When ZCE is "0", the OATT is changed immediately. DATA(HEX) ATT Level 58H 0dB Default 57H -0.75dB 56H -1.5dB * * 3DH -20.25dB 3CH -21.0dB 3BH -21.75dB * * 03H -63.75dB 02H -64.5dB 01H -65.25dB 00H MUTE Table 25. Attenuation value of Output Digital Volume
MS0140-E-01 - 45 -
2002/07
ASAHI KASEI
[AK4564]
SYSTEM DESIGN
Figure 28 shows the system connection diagram. An evaluation board (AKD4564) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
+2.65.5V Analog Supply
1k 100p 100p 1k C3 C3 1 10k PREOL 48 PRENL 47 EXTL 46 INTL 45 + MRF 44 MPWR 43 C1 MVDD 42 MVSS 41 INTR 40 EXTR 39 PRENR 38 PREOR 37 10k
C1: 0.1F C2: 10F
C2 + 680
C2 + C3 C3
C2 + 680
C3: 0.22F
1 SP0
BEEP1 36 MIN 35 MOUT 34 VCOM 33 + C1 C1 + C2 + 2.2
Speaker
2 MUTE 3 SP1 4 PDN
+2.63.6V Analog Supply
+ C2
5 SVDD C1 6 SVSS 7 BCLK 8 MCLK 9 LRCK
AK4564
AVDD 32 AVSS 31 HVCM 30 MUTET 29 HVDD 28 HPR 27 HPL 26 4.7
+2.63.6V Analog Supply
+
C1 C1 + +
2.2
C2 +
+2.65.5V Analog Supply Headphone
20 ROUT1
24 ROUT2
DSP and P
10 CDTI 11 CSN 22 LOUT2 18 LOUT1 12 CCLK 15 DVDD 14 SDTO 16 DVSS 13 SDTI 17 LIN1
BEEP2 25 C1 10 C1 10
C1 C2 + 10
Figure 28. System Connection Diagram
MS0140-E-01 - 46 -
23 RIN2
19 RIN1
21 LIN2
2002/07
ASAHI KASEI
[AK4564]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 37 25
1.70Max 0.13 0.13
1.40 0.05 24 9.0 0.2
48 1 0.22 0.08 12
13
7.0
0.16 0.07 0.5 0.10 M
0 10
0.10
n Package & Lead frame material
0.5 0.2
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb free)
MS0140-E-01 - 47 -
2002/07
ASAHI KASEI
[AK4564]
MARKING
AK4564VQ XXXXXXX
1
XXXXXXXX: Date code identifier IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0140-E-01 - 48 -
2002/07

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